This invention relates to CMOS/SOI integrated circuit fabrication, and specifically to a method of isolating a gate electrode from active silicon by non-conventional isolation.
Conventional techniques for silicon on insulator (SOI) device isolation include mesa isolation, local oxidation of silicon (LOCOS), and trench isolation.
In the mesa isolation technique, the top silicon layer in the field regions are etched prior to gate oxidation. The active device covers the top and the sidewall of the active areas. The doping density and the crystalline structure at the top silicon surface and the sidewall area are not identical. The gate electrode covers the top silicon to sidewall corner. The gate oxide strength at the corner is weaker than that at the top silicon area. This type of isolation has potential problems because of gate oxide breakdown and sidewall parasitic transistor leakage currents.
The LOCOS technique is the most common isolation process. A thin oxide layer is grown on the field region and a relatively thick layer of silicon nitride is deposited over the oxide. The nitride and oxide pad is etched away from the field region. A high temperature oxidation step is performed to convert all of the top silicon layer in the field region to oxide. The nitride and oxide pad is removed, and additional oxide is grown and etched to remove the oxynitride produced by the high temperature thermal oxidation. The LOCOS process consumes too much silicon and requires too large thermal budget to be useful in thin SOI processes.
Trench isolation requires an oxide pad and nitride layer. The nitride, oxide pad and all of the top silicon in the field region are etched and the trenches re-filled with oxide by oxide deposition and a CMP planarization process. This process induces a facet in the active area at the edge of the trench. The gate oxide in the facet is weaker than that at the top of the active area. The threshold voltage of the device in the facet may lower than that at the top active area.
A method of isolating a CMOS device on a silicon on insulator substrate, wherein the substrate includes an insulating layer having a layer of top silicon formed thereon, includes growing a gate oxide layer on the top silicon layer; depositing a first layer of material on the gate oxide layer; removing the first layer of material, the gate oxide layer and the top silicon layer from a device field region; forming an insulating cup about the first layer of material, the gate oxide layer and the top silicon layer; depositing a second layer of material over the first layer of material and the insulating cup; etching the first layer of material and the second layer of material to form a gate electrode; implanting ions to form a source region and a drain region; passivating the structure; and metallizing the structure.
An object of the invention is to eliminate the problems of mesa isolation, LOCOS, and trench isolation for SOI devices.
Another object of the invention is to provide a sidewall transistor having a high threshold voltage.
A further object of the invention is to provide a simplified device isolation method using minimal silicon.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.